Sentrale verwerkingseenheid: Verskil tussen weergawes

 

'n '''Sentrale verwerkingseenheid''' ('''SVE'''), of '''hoofverwerkingseenheid''' is die komponent in 'n [[Digitale stroombaan|digitale rekenaars]] wat [[instruksies]] en [[data]] in rekenaarprogramme vervat vertaal en verwerk SVE's verleen die fundamentele eienskap van [[rekenaarprogrammering|programeerbaarheid]] aan [[rekenaar]]s saam met [[primêre stoorgeheue]] en [[toevoer/afvoer]] fasiliteite. 'n SVE wat vervaardig word deur van [[geïntegreerde stroombaan|geïntegreerde stroombane]] gebruik te maak staan ook as 'n [[mikroverwerker]] bekend. Sedert die middel sewentigs het enkelskyf mikroverwerkers byna alle ander soorte SVE's vervang.

 

== Geskiedenis ==

 

Die eerste rekenaars soos [[ENIAC]] moes fisies herbedraad word om verskillende take uit te voer. Hierdie masjiene is dikwels na verwys as ''vaste-program rekenaars'', aangesien hulle fisies heropgestel moes word om 'n ander program te kon uitvoer. Sedertdien word die begrip '''SVE''' gebruik om te verwys na 'n toestel vir die uitvoer van programmatuur. Die vroegste toestelle wat met reg SVE's genoem kon word, kon eers aangetref word in die eerste rekenaars met gestoorde programme.

 

=== Diskrete transistor en Geïntegreerde stroombaan SVE's ===

 

Die kompleksiteit van SVE-ontwerpe het toegeneem soos wat verskeie nuwe tegnologieë dit moontlik gemaak het om kleiner en meer betroubare elektroniese toestelle te bou. Die eerste sodanige verbetering het plaasgevind met die aankoms van die [[transistor]]. Transistor-SVE's het dit moontlik gemaak om betroubare SVE's op een of verskeie [[gedrukte stroombaan]]borde met diskrete komponente daarop te bou. Die volgende groot ontwikkeling was die [[geïntegreerde stroombaan]] wat dit moontlik gemaak het om 'n groot aantal transistors op 'n enkele [[halfgeleier]]gebaseerde skyf te vervaardig. Eers was dit slegs moontlik om baie basiese nie-gespesialiseerde digitale stroombane soos [[Logiese_hek#NOF-hekke|NOF-hekke]] te vervaardig. SVE's wat uit sulke boublokke saamgestel is, word kleinskaalse integrasietoestelle genoem. Kleinskaalse geïntegreerde stroombane soos dié wat in die [[Apollo]] begeleidingsrekenaars gebruik is, het bestaan uit tiene transistors. Om 'n volle SVE uit kleinskaal geïntegreerde stroombane te bou het steeds duisende indiwiduele skyfies geverg maar was nogtans 'n groot sprong bo die transistorgebaseerde SVE's in terme van die kragverbruik en spasieverbruik. Tegnologiese vordering in die vervaardiging van geïntegreerde stroombane het daartoe gelei dat honderde en later duisende transistors (Mediumskaal- en grootskaalse integrasie) op 'n enkele silikonskyf geplaas kon word en meegebring dat die aantal nodige geïntegreerde stroombane (GS) om 'n SVE te bou, verminder kon word. In 1964 het [[IBM]] hulle System/360 rekenaarargitektuur bekendgestel wat in 'n reeks rekenaars gebruik is wat dieselfde programme met verskillende snelheid en verrigting kon uitvoer. Dit was 'n betekenisvolle stap op daardie tydstip toe die meeste elektroniese rekenaars nie met mekaar versoenbaar was nie, selfs al is hulle deur dieselfde vervaardiger gebou. Om hierdie verbetering moontlik te maak, het IBM die konsep van 'n [[mikroprogram]] gebruik, wat steeds in moderne SVE's gebruik word. Die System/360 argitektuur was so gewild dat dit die [[hoofraamrekenaar]]mark vir die daaropvolgende dekades gedomineer het en 'n nalatenskap daargelaat het wat voortgesit is in soortgelyke moderne rekenaars soos die IBM zSeries.

 

=== Mikroverwerkers ===

 

Die bekendstelling van die [[mikroverwerker]] in die 1970's het die ontwerp van SVE's beduidend beïnvloed. Sedert die bekendstelling van die eerste mikroverwerker (die [[Intel 4004]]) in 1970 en die eerste algemeen gebruikte mikroverwerker (die [[Intel 8080]]) in 1974, het hierdie klas SVE's bykans alle implementerings van verwerkingseenhede vervang. Soos al hoe kleiner transistors op GIS'e gebou kon word, het die kompleksiteit en aantal transistors op 'n enkele SVE dramaties toegeneem. Hierdie waargenome neiging staan alom bekend as [[Moore se wet]], wat tot op datum 'n akkurate vooruitskatting was vir die groeiende vermoëns van SVE's (en ander GIS'e).

The instruction that the CPU fetches from memory is used to determine what the CPU is to do. In the '''decode''' step, the instruction is broken up into parts that have significance to other portions of the CPU. The way in which the numerical instruction value is interpreted is defined by the CPU's [[instruction set architecture]] ('''ISA'''). <ref>Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the "type" of CPU. For example, a "[[PowerPC]] CPU" uses some variant of the PowerPC ISA. Some CPUs, like the Intel [[Itanium]], can actually interpret instructions for more than one ISA; however this is often accomplished by software means rather than by designing the hardware to directly support both interfaces. (See [[emulator]])</ref> Often, one group of numbers in the instruction, called the [[opcode]], indicates which operation to perform. The remaining parts of the number usually provide information required for that instruction, such as operands for an [[addition]] operation. Such operands may be given as a constant value (called an immediate value), or as a place to locate a value: a [[processor register|register]] or a [[memory address]], as determined by some [[addressing mode]]. In older designs the portions of the CPU responsible for instruction decoding were unchangeable hardware devices. However, in more abstract and complicated CPUs and ISAs, a [[microprogram]] is often used to assist in translating instructions into various configuration signals for the CPU. This microprogram is sometimes rewritable so that it can be modified to change the way the CPU decodes instructions even after it has been manufactured.

 

 

After the fetch and decode steps, the '''execute''' step is performed. During this step, various portions of the CPU are connected so they can perform the desired operation. If, for instance, an addition operation was requested, an [[arithmetic logic unit]] ('''ALU''') will be connected to a set of inputs and a set of outputs. The inputs provide the numbers to be added, and the outputs will contain the final sum. The ALU contains the circuitry to perform simple arithmetic and logical operations on the inputs (like addition and [[bitwise operation]]s). If the addition operation produces a result too large for the CPU to handle, an [[arithmetic overflow]] flag in a flags register may also be set (see the discussion of integer range below).

The way a CPU represents numbers is a design choice that affects the most basic ways in which the device functions. Some early digital computers used an electrical model of the common [[decimal]] (base ten) [[numeral system]] to represent numbers internally. A few other computers have used more exotic numeral systems like [[ternary logic|ternary]] (base three). Nearly all modern CPUs represent numbers in [[Binary numeral system|binary]] form, with each digit being represented by some two-valued physical quantity such as a "high" or "low" [[volt]]age. <ref>The physical concept of [[voltage]] is an analog one by its nature, practically having an infinite range of possible values. For the purpose of physical representation of binary numbers, set ranges of voltages are defined as one or zero. These ranges are usually influenced by the operational parameters of the switching elements used to create the CPU, such as a [[transistor]]'s threshold level.</ref>

 

 

Related to number representation is the size and precision of numbers that a CPU can represent. In the case of a binary CPU, a '''bit''' refers to one significant place in the numbers a CPU deals with. The number of bits (or numeral places) a CPU uses to represent numbers is often called "[[Word (computer science)|word size]]", "bit width", "data path width", or "integer precision" when dealing with strictly integer numbers (as opposed to floating point). This number differs between architectures, and often within different parts of the very same CPU. For example, an [[8-bit]] CPU deals with a range of numbers that can be represented by eight binary digits (each digit having two possible values), that is, 2⁸ or 256 discrete numbers. In effect, integer size sets a hardware limit on the range of integers the software run by the CPU can utilize. <ref>While a CPU's integer size sets a limit on integer ranges, this can (and often is) overcome using a combination of software and hardware techniques. By using additional memory, software can represent integers many magnitudes larger than the CPU can. Sometimes the CPU's ISA will even facilitate operations on integers larger that it can natively represent by providing instructions to make large integer arithmetic relatively quick. While this method of dealing with large integers is somewhat slower than utilizing a CPU with higher integer size, it is a reasonable trade-off in cases where natively supporting the full integer range needed would be cost-prohibitive. See [[Arbitrary-precision arithmetic]] for more details on purely software-supported arbitrary-sized integers.</ref>

 

=== Clock rate ===

{{main|Clock rate}}

 

 

=== Parallelism ===

{{main|Parallel computing}}

 

 

==== ILP: Instruction pipelining and superscalar architecture ====

{{main articles|[[Instruction pipelining]], [[Superscalar]]}}

 

Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict. To cope with this, additional care must be taken to check for these sorts of conditions and delay a portion of the instruction pipeline if this occurs. Naturally, accomplishing this requires additional circuitry, so pipelined processors are more complex than subscalar ones (though not very significantly so). A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more than one clock cycle in a stage).

 

 

Further improvement upon the idea of instruction pipelining led to the development of a method that decreases the idle time of CPU components even further. Designs that are said to be '''superscalar''' include a long instruction pipeline and multiple identical execution units. In a superscalar pipeline, multiple instructions are read and passed to a dispatcher, which decides whether or not the instructions can be executed in parallel (simultaneously). If so they are dispatched to available execution units, resulting in the ability for several instructions to be executed simultaneously. In general, the more instructions a superscalar CPU is able to dispatch simultaneously to waiting execution units, the more instructions will be completed in a given cycle.